1. Field of the Invention
This invention relates to an improved superconductive Josephson junction logic circuit. More particularly, this invention relates to a new and improved Josephson junction logic latch circuit.
2. Related Applications
This invention is in part related to our co-pending application entitled "Three Josephson Junction Direct-Coupled Isolation Circuit", Ser. No. 288,148 filed Aug. 31, 1981, now U.S. Pat. No. 4,413,196 which shows and describes a novel OR logic circuit which provides an amplified output. Further, this invention relates in part to our co-pending application entitled "A Four Josephson Junction Direct-Coupled AND Gate Circuit", Ser. No. 298,149 filed Aug. 31, 1981, now U.S. Pat. No. 4,413,197 which shows and describes an AND logic circuit which also provides amplification.
3. Description of the Prior Art
Prior art logic circuits which employ Josephson junction devices are presently classified in U.S. Class 307, sub class 306 with superconductive devices. The prior art includes A. Davidson's article entitled "A Josephson Latch", IEEE Journal of Solid State Circuits Volume SC-13 No. 5, October, 1978 at pages 583 to 590. This 1978 IEEE article shows a Josephson junction latch which includes ten interferometers and each interferometer comprises a plurality of Josephson junctions. A block diagram logic circuit shows the equivalent of a flip-flop which requires a separate d.c. power source to store one bit. Further, the block diagram logic circuit requires a self-gating AND gate (SGA). The input signals to the SGA are described as being provided by a flip-flop. The signals from the flip-flop are not in usable form as true or complement output signal levels.
The prior art also includes H. C. Jones' and T. R. Gheewalas' article entitles "Ultra High Speed Josephson Latch", IEEE International Conference on Circuits and Computers, Volume 2, 1980 at pages 884 to 886. A two-port data latch circuit is shown as FIG. 2 on pages 885. This latch circuit is a modification of the afore-mentioned Davidson article in that the flip-flop or storage loop does not require a separate d.c. power supply. The schematic circuit shows a slave circuit in the place of the SGA circuit of the afore-mentioned article. This latch circuit employs a modified input AND-OR gate system to provide input isolation to the input AND gate.
Both of the above prior art circuits employ interferometers in the input and output which are inductively coupled devices.
It would be desirable to provide a simplified Josephson junction logic circuit which can be employed as a logic module building block and which provides two direct-coupled amplified outputs representative of a true quantity and a complement of the true quantity.